SEALSQ to Unveil and Demonstrate Two New Quantum-Resistant Chips and a Post-Quantum ASIC Design Concept at electronica 2026 Hall C6, Booth 670
SEALSQ will unveil two quantum-resistant chips, VaultIC409 and QVault TPM, plus the QASIC post-quantum ASIC design concept at electronica 2026 in Munich, Nov 10-13 (Hall C6, Booth 670). VaultIC409, built on the QS7001 platform, is in Common Criteria EAL5+ certification with engineering samples planned for Q2 2027; QVault TPM embeds ML-KEM and ML-DSA in silicon and is on a FIPS 140-3 and TCG certification path with wolfSSL support already added. QASIC is a custom post-quantum ASIC design offering from subsidiary IC'Alps, which SEALSQ acquired in August 2025.
Key figures
- Certification status
- VaultIC409 undergoing Common Criteria EAL5+ certification; QVault TPM on FIPS 140-3 and TCG certification path
- Engineering samples timeline
- Q2 2027
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